1. Field of the Invention
This invention relates to a semiconductor memory device having a memory cell array including nonvolatile semiconductor memory elements and a dummy cell array, and more particularly to a semiconductor memory device in which data programming can be permitted only once.
2. Description of the Related Art
A nonvolatile semiconductor memory device, particularly an EPROM whose memory cells are double gate nonvolatile MOS transistors with a floating gate and a control gate, allows data to be rewritten thereinto. Because of this feature, the EPROMs have been used in various types of computer systems. If electrons are stored on the floating gate of the double gate MOS transistor, the threshold voltage thereof is high. With such a high threshold voltage, the MOS transistor will not be conductive when a high level voltage, for example, +5 V is applied to the control gate. But when no electron is stored on the floating gate, the threshold voltage is maintained its initial low voltage. If the high level voltage is applied to the control gate, the MOS transistor is conductive. If a binary "1" and "0" are respectively assigned to the conductive and nonconductive states of the memory cell, the data can be detected. In this way, data can be stored in the memory cell. When a voltage of, for example, 12.5 V which is sufficiently higher than a normal power source voltage of 5 V is applied to the control gate and drain, electrons are injected into the floating gate. When such a high voltage is applied, impact ionization occurs in the channel region near the drain, thus causing electrons of the hole-electron pairs generated by the impact ionization to be injected into the floating gate. Electrons thus injected into the floating gate are held inside the floating gate unless data erasing operation is effected.
FIG. 1 is a circuit diagram of a conventional semiconductor memory device having the nonvolatile memory elements described above as memory cell. In FIG. 1, WL1 to WLm denote row lines which are connected to receive row selection signals from a row decoder (not shown), and COL1 to COLn denote column selection lines to which column selection signals from a column decoder (not shown) are supplied. Column selection MOS transistors C1 to Cn are driven by supplying the column selection signals to the column selection lines COL1 to COLn. The MOS transistors C1 to Cn are connected at one end to column lines BL1 to BLn, respectively, and at the other end to circuit node A.
Memory cells M11 to Mmn formed of double gate MOS transistors each having a floating gate are provided in respective intersections of the row lines WL1 to WLm and column lines COL1 to COLn. Each of the control gates of MOS transistors M11 to Mmn is connected to a corresponding one of the row lines, each drain is connected to a corresponding one of the column lines, and each source is connected to ground potential terminal VS, for example ground.
A sense amplifier S/A and one end of a data programming MOS transistor P are connected to circuit node A. The other end of the MOS transistor P is connected to programming power source terminal VP, and the gate thereof is connected to receive a data setting signal DIN for permitting data programming operation. The data setting signal DIN is set to a low or high potential level according to the contents of data to be programmed.
A high voltage of, for example, 12.5 V is applied to the terminal VP, when data is written in the memory cells. When data "0" is written in the memory cell M11, for example, in the memory device of FIG. 1, the signal line DIN and a column selection line COL1 are set to a high potential level so that the MOS transistors P and C1 are turned on. Correspondingly, the high level voltage is applied to the column selection line BL1. At the same time, the row line WL1 is selected and set to a high potential level. As a result, impact ionization occurs in the channel region near the drain of the memory cell M11, causing electrons to be injected into the floating gate thereof. Thus, the memory cell M11 is set into the "0", that is, data "0" is programmed into the memory cell M11.
In order to program data "1" into the memory cell M11, the signal DIN is kept at a low potential level so as to keep the MOS transistor P in a nonconductive state. Thus, the column line BL1 is maintained at a low potential level so that the floating gate of the memory cell M11 is kept in the neutral state.
In the semiconductor memory device shown in FIG. 1, stored electrons in the floating gate of the memory cell can be ejected from the floating gate by exposing the memory device to ultraviolet light to the memory device. The floating gate is returned into the neutral state and therefore data can be programmed again.
FIG. 2 schematically shows the entire construction of a memory circuit or a chip including the semiconductor memory array and peripheral circuits thereof. The memory circuit of FIG. 2 includes control circuit 1 for controlling an operating condition of the memory chip. Chip enable signal CE and output enable signal OE are supplied to the control circuit 1, the chip enable signal CE being used to control the operating condition of the memory chip and determine whether or not the memory chip is set in the standby mode, and the output enable signal OE being used to control an output buffer circuit so as to set an output buffer section of the output buffer into a high impedance state. The semiconductor chip is maintained in an active mode, when the chip enabling signal CE is kept at "0" level. In contrast, the semiconductor chip is maintained in the standby mode, when the chip enable signal CE is kept at "1" level. In the standby mode, a consumption current consumed in the semiconductor chip is decreased to be kept at a power-down condition. In this condition, no data is outputted from the semiconductor chip and an output terminal (the output section) is set to be at the high impedance state. The output terminals are set to be at a high impedance state, even if the output enable signal OE is kept at "0" level or "1" level, when the chip enable signal CE is kept at "1" level. In the active mode wherein the chip enable signal CE is kept at "0" level, data is outputted from the output buffer, when the output enable signal OE is set to "0" level. On the other hand, even if the semiconductor chip is maintained in the active mode wherein the chip enable signal CE is kept at "0" level, if the output enable signal OE which is kept at "1" level causes the output buffer to set to the high impedance state, no data is outputted from the buffer. The control circuit 1 generates CE and OE control signals in response to the chip enable signal CE and the output enable signal OE. The CE and OE control signals are used to control the operation of column address buffer 2, row address buffer 3, column decoder 4, row decoder 5 and output buffer 6. As shown in FIG. 1, memory cell array 7 is constituted by the nonvolatile memory cells arranged in the matrix form of the rows and columns, and column gate 8 is constituted by the column selection MOS transistors C1 to Cn.
In the above semiconductor memory device or EPROM, it is possible to erase data by use of ultraviolet rays and reprogram data electrically. However, in general, semiconductor user scarcely so use EPROM as to erase initial data and write new data after the EPROM having the initial data had been used. That is, EPROM is always used such that data programming operation is effected only once. With such a market taken into consideration, semiconductor memory devices packed cheep plastic packages are manufactured instead of expensive ceramic packages each having a window for permitting transmission of ultraviolet rays. Such semiconductor memory device is the same chip as the EPROM but is limited to be programmed only once because the chip is packed in the plastic package which prevents transmission of ultraviolet rays. So, such semiconductor memory devices are so called as one time PROMs (OTP).
In such a one time PROM, if the chip is once packed in the plastic package, data cannot be erased. Therefore it is necessary to ship the semiconductor memory devices with no electrons injected in the floating gate of each memory cell, or with data "1" stored in all the memory cells. For this reason, the programming test of programming data "0" cannot be effected after the packaging and before shipment. Consequently, semiconductor maker cannot test the electrical characteristics such as data readout speed of the devices after the memory chip had been packaged in the plastic package.